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? semiconductor components industries, llc, 2016 february, 2016 ? rev. 0 1 publication order number: ncp81243/d ncp81243 dual output 3 & 2 phase controller with single intel proprietary interface for desktop and notebook cpu applications the ncp81243 dual output three plus two phase buck solutions are optimized for intel ? ?s imvp8 cpus. the ncp81243 offer five pwm drive signals that can be configured in multiple setups. the controller combines true differential voltage sensing, differential inductor dcr current sensing, input voltage feed?forward, and adaptive voltage positioning to provide accurately regulated power for both desktop and notebook applications. the control system is based on dual?edge pulse?width modulation (pwm) combined with dcr current sensing providing an ultra fast initial response to dynamic load events and reduced system cost. the ncp81243 provides the mechanism to shed phases during light load operation and can auto frequency scale in light load conditions while maintaining excellent transient performance. dual high performance operational error amplifiers are provided to simplify compensation of the complete system. patented dynamic reference injection further simplifies loop compensation by eliminating the need to compromise between closed?loop transient response and dynamic vid performance. patented total current summing provides highly accurate current monitoring for droop and digital current monitoring. features ? meets intel?s imvp8 specification ? current mode dual edge modulation for fast initial response to transient loading ? dual high performance operational error amplifier ? one digital soft start ramp for both rails ? dynamic reference injection ? accurate total summing current amplifier ? dac with droop feed?forward injection ? dual high impedance differential voltage and total current sense amplifiers ? phase?to?phase dynamic current balancing ? ?lossless? dcr current sensing for current balancing ? summed compensated inductor current sensing for droop ? true differential current balancing sense amplifiers for each phase ? adaptive voltage positioning (avp) ? switching frequency range of 300 khz ? 1.4 mhz ? startup into pre?charged loads while avoiding false ovp ? pin programmable power saving phase shedding ? vin feed forward ramp slope ? over voltage protection (ovp) & under voltage protection (uvp) ? over current protection (ocp) ? dual power good output with internal delays ? these devices are pb?free, halogen free/bfr free and are rohs compliant applications ? desktop & notebook processors ? gaming marking diagram www. onsemi.com 52 1 qfn52 mn suffix case 485be ncp81243 = specific device code f = wafer fab a = assembly site wl = lot id yy = year ww = work week = pb?free package ncp81243 fawlyyww device package shipping ? ordering information NCP81243MNTXG qfn52 (pb?free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
ncp81243 www. onsemi.com 2 figure 1. r305 dnp 1 2 c343 dnp 1 c344 dnp 2 1 c345 dnp 2 1 r306 dnp 1 2 r307 dnp 1 2 c86 1uf 2 1 c346 dnp 2 1 r309 dnp 1 2 c69 1000pf c340 1000pf rosc 2 diffa compa r238 1.00k 1 2 j76 fba c232 680pf 1 2 j77 1 r240 49.9 1 2 r239 5.1k 1 2 vccio j78 1 c234 10pf 1 2 c233 2.2nf 1 2 c94 0.1uf 1 1 csref tsense iout sdio alert# sclk vcc vsn 2 +5v_in diffout csp1 cssum comp csp2 csp3 cscomp tsense cscomp csp2 fb fb comp csp1a diffout csp2a csp3 r272 dnp +5v_in 1 ilim vsp vboota/adda ser_en j39 2 r19 dnp 1 1 j95 2pin 1 2 r3 0.0 1 2 r34 100 1 2 j42 2 r131 75.0k 1 2 j28 1 r127 dnp 1 1 2 r155 130 1 r40 1.0k 2 1 j21 1 c61 0.1uf 1 2 r132 165k 1 2 c85 0.1uf 1 2 r27 4.7k 1 2 r37 1.00k 1 2 2 r156 54.9 1 r296 dnp 1 2 rt126 220k iccmaxa j41 2 c79 1uf 1 1 psys feed for ncp81203a c56 680f 1 2 r297 dnp 2 1 j56 1 j13 2pin 1 2 r8 10.0 1 2 c83 0.1uf 1 2 ser_vr_rdy {4} j8 j45 1 r16 dnp 2 1 j32 j29 2 r9 4.7k 1 2 r38 34.2k 1 2 c51 1nf 1 1 j1 5pin c155 1.2nf 2 1 r18 40k 1 2 r43 5.1k 1 2 j47 1 2 r138 124k 1 2 j26 1 r71 2.2 1 2 c156 620pf cssum 1 2 r159 dnp 1 r12 10.0 1 2 c82 10nf 2 1 r154 32k 2 1 r10 4.7k 1 2 r50 49.9 1 2 rt130 220k r184 20k 2 1 r125 0.0 2 1 c80 0.1uf 1 2 r4 10.0 1 2 r303 2.10k 1 2 c55 2.2nf 1 2 j2 5pin 2 r158 dnp 1 c341 2.2nf 1 2 jp5 etch j62 1 j59 20pin 2row 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 r2 0.0 1 2 r139 124k 1 2 2 r160 dnp 1 j63 1 j61 1 c57 10pf 1 2 2 r157 75 1 j27 2 j40 1 r140 124k 1 2 r48 100 1 2 +5v_in v_1p05_vccp +vdc_in r304 2.10k 1 2 label as "digital interface" place close to l1 main rail vsense core vcccore c342 2.2nf 12 place close to l1 vr_rdy {4} alert# {5} sdio {5} vr_hot {4} vsscore_sense {5} sclk {5} vsn {4} vsp {4} vcccore_sense {5} swn3 {3} csn3 {3} swn1 {3} csn1 {3} dron {3} swn2 {3} csn2 {3} enable {4} pwm1a pwm2a r241 20k 1 1 +5v_in vboot/add r242 47k 2 1 iccmaxa r243 68k 2 1 iccmax c347 dnp 2 1 r308 dnp 1 2 c239 0.1uf 1 2 r255 10.0 1 2 r260 4.7k 1 2 swn2a{4} csn2a{4} r262 124k 1 2 vrmp vcc pwm2 r244 75k 2 1 pwm3 pwm1 r187 390 2 1 2 r300 0 1 2 fsw=400k vboot=1v; address main rail=0, address aux=1 sr=10mv/us, 4+1 config csref csp2 csn2 csn3 c235 0.1uf csp3 1 u16a nl37wz07 1 7 2 8 tsensea csn1 rt131 220k r245 0.0 4 1 place close to l1 auxiliary rail csp1 r246 15k 2 1 vcccore iouta c236 0.1uf 1 2 r247 21.5k 1 2 j79 1 tsensea r249 100 1 2 r248 0.0 1 2 c237 1nf 2 1 j80 2pin 1 2 r251 100 1 2 r250 0.0 12 vsensegt vssgt_sense {5} vccgt vsna {4} vspa{4} vccgt_sense {5} vsna vspa 2 diffa fba cscompa compa r32 15k ilima 1 2 cssuma csrefa csp2a csp1a csn2a v_1p05_vccp vccgt csrefa cssuma csp1a csp2a csn1a ilim ilima j81 cscompa r253 165k 1 2 r252 75.0k 1 2 r256 4.7k 1 2 j82 r257 23k 1 2 c240 1nf 1 1 c241 360pf 2 1 c242 0.1uf 1 2 rt132 220k r261 10.0 1 2 r263 136k 12 place close to l1 csn1a{4} phase detection swn1a{4} u6 ncp81243?dnp en 2 1 iout sdio 3 alert 4 sclk 5 vr_rdy 6 vcc 7 rosc 8 vrmp 9 prog pin 10 tsensea 11 vrhot 12 iouta 13 2 vsna 14 vspa 15 diffa 16 fba 17 compa 18 cscompa 19 ilima 20 cssuma 21 csrefa 22 csp2a 23 csn2a 24 csp1a 25 csn1a vboota/addra 27 vboot/addr 28 iccmaxa 29 pwm1a 30 pwm2a 31 pwm3 32 pwm2 33 pwm1 34 drvon 35 iccmax 36 tsense 37 csn1 38 csp1 39 26 csn2 40 csp2 41 csn3 42 csp3 43 csref 44 cscum 45 ilim 46 cscomp 47 comp 48 fb 49 diff 50 vsp 51 vsn 52 gnd ser_en 53
ncp81243 www. onsemi.com 3 figure 2. r305 dnp 1 2 c343 dnp 1 c344 dnp 2 1 c345 dnp 2 1 r306 dnp 1 2 r307 dnp 1 2 c86 1uf 2 1 c346 dnp 2 1 r309 dnp 1 2 c69 1000pf c340 1000pf rosc 2 diffa compa r238 1.00k 1 2 j76 fba c232 680pf 1 2 j77 1 r240 49.9 1 2 r239 5.1k 1 2 vccio j78 1 c234 10pf 1 2 c233 2.2nf 1 2 c94 0.1uf 1 1 csref tsense iout sdio alert# sclk vcc vsn 2 +5v_in diffout csp1 cssum comp csp2 csp3 cscomp tsense cscomp csp2 fb fb comp csp1a diffout csp2a csp3 r272 dnp +5v_in 1 ilim vsp vboota/adda ser_en j39 2 r19 dnp 1 1 j95 2pin 1 2 r3 0.0 1 2 r34 100 1 2 j42 2 r131 75.0k 1 2 j28 1 r127 dnp 1 1 2 r155 130 1 r40 1.0k 2 1 j21 1 c61 0.1uf 1 2 r132 165k 1 2 c85 0.1uf 1 2 r27 4.7k 1 2 r37 1.00k 1 2 2 r156 54.9 1 r296 dnp 1 2 rt126 220k iccmaxa j41 2 c79 1uf 1 1 psys feed for ncp81203a c56 680f 1 2 r297 dnp 2 1 j56 1 j13 2pin 1 2 r8 10.0 1 2 c83 0.1uf 1 2 ser_vr_rdy {4} j8 j45 1 r16 dnp 2 1 j32 j29 2 r9 4.7k 1 2 r38 34.2k 1 2 c51 1nf 1 1 j1 5pin c155 1.2nf 2 1 r18 40k 1 2 r43 5.1k 1 2 j47 1 2 r138 124k 1 2 j26 1 r71 2.2 1 2 c156 620pf cssum 1 2 r159 dnp 1 r12 10.0 1 2 c82 10nf 2 1 r154 32k 2 1 r10 4.7k 1 2 r50 49.9 1 2 rt130 220k r184 20k 2 1 r125 0.0 2 1 c80 0.1uf 1 2 r4 10.0 1 2 r303 2.10k 1 2 c55 2.2nf 1 2 j2 5pin 2 r158 dnp 1 c341 2.2nf 1 2 jp5 etch j62 1 j59 20pin 2row 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 r2 0.0 1 2 r139 124k 1 2 2 r160 dnp 1 j63 1 j61 1 c57 10pf 1 2 2 r157 75 1 j27 2 j40 1 r140 124k 1 2 r48 100 1 2 +5v_in v_1p05_vccp +vdc_in r304 2.10k 1 2 label as "digital interface" place close to l1 main rail vsense core vcccore c342 2.2nf 12 place close to l1 vr_rdy {4} alert# {5} sdio {5} vr_hot {4} vsscore_sense {5} sclk {5} vsn {4} vsp {4} vcccore_sense {5} swn3 {3} csn3 {3} swn1 {3} csn1 {3} dron {3} swn2 {3} csn2 {3} enable {4} pwm1a pwm2a r241 20k 1 1 +5v_in vboot/add r242 47k 2 1 iccmaxa r243 68k 2 1 iccmax c347 dnp 2 1 r308 dnp 1 2 c239 0.1uf 1 2 r255 10.0 1 2 r260 4.7k 1 2 swn2a{4} csn2a{4} r262 124k 1 2 vrmp vcc pwm2 r244 75k 2 1 pwm3 pwm1 r187 390 2 1 2 r300 0 1 2 fsw=400k vboot=1v; address main rail=0, address aux=1 sr=10mv/us, 4+1 config csref csp2 csn2 csn3 c235 0.1uf csp3 1 u16a nl37wz07 1 7 2 8 tsensea csn1 rt131 220k r245 0.0 4 1 place close to l1 auxiliary rail csp1 r246 15k 2 1 vcccore iouta c236 0.1uf 1 2 r247 21.5k 1 2 j79 1 tsensea r249 100 1 2 r248 0.0 1 2 c237 1nf 2 1 j80 2pin 1 2 r251 100 1 2 r250 0.0 12 vsensegt vssgt_sense {5} vccgt vsna {4} vspa{4} vccgt_sense {5} vsna vspa 2 diffa fba cscompa compa r32 15k ilima 1 2 cssuma csrefa csp2a csp1a csn2a v_1p05_vccp vccgt csrefa cssuma csp1a csp2a csn1a ilim ilima j81 cscompa r253 165k 1 2 r252 75.0k 1 2 r256 4.7k 1 2 j82 r257 23k 1 2 c240 1nf 1 1 c241 360pf 2 1 c242 0.1uf 1 2 rt132 220k r261 10.0 1 2 r263 136k 12 place close to l1 csn1a{4} phase detection swn1a{4} u6 ncp81243?dnp en 2 1 iout sdio 3 alert 4 sclk 5 vr_rdy 6 vcc 7 rosc 8 vrmp 9 prog pin 10 tsensea 11 vrhot 12 iouta 13 2 vsna 14 vspa 15 diffa 16 fba 17 compa 18 cscompa 19 ilima 20 cssuma 21 csrefa 22 csp2a 23 csn2a 24 csp1a 25 csn1a vboota/addra 27 vboot/addr 28 iccmaxa 29 pwm1a 30 pwm2a 31 pwm3 32 pwm2 33 pwm1 34 drvon 35 iccmax 36 tsense 37 csn1 38 csp1 39 26 csn2 40 csp2 41 csn3 42 csp3 43 csref 44 cscum 45 ilim 46 cscomp 47 comp 48 fb 49 diff 50 vsp 51 vsn 52 gnd ser_en 53
ncp81243 www. onsemi.com 4 adc diffamp ovp dac gnd csref error amp - + thermal monitor data registers intel proprietary interface inter face dac current measurement & limit cs amp mux current balance pwm generators power state stage uvlo & en ramp generators vr ready comparator enable enable enable compa ovp enable vsn vsp tsense vrhot sdio alert sclk vrdy vrmp pwm2a pwm1a dron enable vcc csp1a csn1a csp2a csn2a diffout fb comp ilim iout cssum csref cscomp vsp vsn ovp enable vsp vsn dac dac iph2a iph1a ramp1a ramp2a ncp81243 rosc aux dac aux dac vspa vsna aux dac aux ovp vspa vsna ovpa tsensea aux diffamp dac gnd csrefa error amp - + current measurement & limit aux cs amp vsna vspa diffouta fba compa ilima iouta cssuma csrefa cscompa vsp-vsn vspa-vsna tsense tsensea imax imaxa iout iouta addr addra current balance pwm generators power state stage enable comp ovp pwm3 pwm2 pwm1 csp1 csn1 csp3 csn3 csp2 csn2 iph3 iph2 iph1 ramp1 ramp2 ramp3 gnd ph_config vboot vboota addr addra figure 3. 3 + 2 block diagram
ncp81243 www. onsemi.com 5 figure 4. 4 + 1 block diagram adc diffamp ovp dac gnd csref error amp - + thermal monitor data registers intel proprietary interface inter face dac current measurement & limit cs amp mux current sense pwm generator power state stage uvlo & en ramp generators vr ready comparator enable enable enable compa ovp enable vsn vsp tsense vrhot sdio alert sclk vrdy vrmp pwm2a pwm1a dron enable vcc csp1a csn1a csp2a csn2a diffout fb comp ilim iout cssum csref cscomp vsp vsn ovp enable vsp vsn dac dac iph2a iph1a ramp1a ramp2a ncp81243 rosc aux dac aux dac vspa vsna aux dac aux ovp vspa vsna ovpa tsensea aux diffamp dac gnd csrefa error amp - + current measurement & limit aux cs amp vsna vspa diffouta fba compa ilima iouta cssuma csrefa cscompa vsp-vsn vspa-vsna tsense tsensea imax imaxa iout iouta addr addra current balance pwm generators power state stage enable comp ovp pwm3 pwm2 pwm1 csp1 csn1 csp3 csn3 csp2 csn2 iph3 iph2 iph1 ramp1 ramp2 ramp3 gnd ph_config vboot vboota addr addra
ncp81243 www. onsemi.com 6 figure 5. pinout pwm1 pwm2 pwm3 pwm1a pwm2a 12v vcore v auxiliary sda alert sclk vr_rdy enable vrhot rosc ph_config comp fb diffout ilim cscomp cssum comp fb diffout ilim cscomp cssum vrmp gnd vcc 5v dron iout iouta csref csrefa tsense tsensea
ncp81243 www. onsemi.com 7 ncp81243 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 52 51 50 49 48 47 46 45 44 43 42 41 40 14 15 16 17 18 19 20 21 22 23 24 25 26 csp1 csn1 tsense iccmax drvon pwm1 pwm2 pwm3 pwm2a pwm1a iccmaxa vboot/addr vboota/addra vsn vsp diff fb comp cscomp ilim cssum csref csp3 csn3 csp2 csn2 iout en sdio alert# sclk vrdy vcc rosc vrmp ph/fdm/fda/sr tsensea vrhot iouta vsna vspa diffa fba compa cscompa ilima cssuma csrefa csp2a csn2a csp1a csn1a figure 6. table 1. qfn52 pin list description pin no. symbol description 1 iout total output current for main rail. 2 en logic input. logic high enables both rail output and logic low disables both rail output. 3 sdio serial vid data interface 4 alert# serial vid alert#. 5 sclk serial vid clock 6 vrdy open drain output. high output on this pin indicates that the main rail output is regulating. 7 vcc power for the internal control circuits. a decoupling capacitor is connected from this pin to ground. 8 rosc a resistor to ground on this pin will set the oscillator frequency 9 vrmp feed?forward input of vin for the ramp slope compensation. the current fed into this pin is used to control of the ramp of pwm slope 10 ph/fdm/fda/sr a resistor to ground on startup is used to set the phase configuration per rail of the ncp81243 as well as the fast slew rate 11 tsensea temp sense input for auxiliary rail 12 vr_hot open drain output. signals an over temperature event has occurred 13 iouta total output current for the auxiliary rail. 14 vsna differential output voltage sense negative for auxiliary rail 15 vspa differential output voltage sense positive for auxiliary rail 16 diffa output of the auxiliary rail differential remote sense amplifier. 17 fba error amplifier voltage feedback for auxiliary rail output 18 compa output of the error amplifier and the inverting inputs of the pwm comparators for the auxiliary rail output. 19 cscompa output of total current sense amplifier for auxiliary rail output. 20 ilima over current shutdown threshold setting for auxiliary rail l output. resistor to cscomp to set threshold. 21 cssuma inverting input of total current sense amplifier for auxiliary rail output. 22 csrefa total output current sense amplifier reference voltage input for auxiliary rail 23 csp2a non?inverting input to current balance sense amplifier for phase 2 a 24 csn2a inverting input to current balance sense amplifier for phase 2 a 25 csp1a non?inverting input to current balance sense amplifier for phase 1 a 26 csn1a inverting input to current balance sense amplifier for phase 1 a
ncp81243 www. onsemi.com 8 table 1. qfn52 pin list description pin no. description symbol 27 vboota/addra vboot and address aux rail input pin. a resistor to ground on startup is used to vboot and address of the auxiliary rail 28 vboot/addr vboot and address main rail input pin. a resistor to ground on startup is used to vboot and address of the main rail 29 iccmaxa iccmax input for auxiliary rail pin. during start up it is used to program configuration of internal register with a resistor to ground 30 pwm1a pwm 1 auxiliary rail output. 30 pwm1a pwm 1 auxiliary rail output. iccmax input for auxiliary rail pin. 31 pwm2a pwm 2 auxiliary rail output. 32 pwm3 pwm 3 main rail output. 33 pwm2 pwm 2 main rail output. 34 pwm1 pwm 1 main output. 35 drvon bidirectional gate driver enable for external drivers for both main and auxiliary rails. it should be left floating if unused. 36 iccmax iccmax main rail input pin. during start up it is used to program configuration of internal register with a resistor to ground 37 tsense temp sense input for main rail 38 csn1 non?inverting input to current balance sense amplifier for main rail phase 1 39 csp1 non?inverting input to current balance sense amplifier for main rail phase 1 40 csn2 non?inverting input to current balance sense amplifier for main rail phase 2 41 csp2 non?inverting input to current balance sense amplifier for main rail phase 2 42 csn3 non?inverting input to current balance sense amplifier for main rail phase 2 43 csp3 non?inverting input to current balance sense amplifier for main rail phase 2 44 csref total output current sense amplifier reference voltage input for main rail 45 cssum inverting input of total current sense amplifier for main rail output 46 ilim over current shutdown threshold setting for main rail output. resistor to cscomp to set threshold. 47 cscomp output of total current sense amplifier for main rail output 48 comp output of the main rail error amplifier and the inverting input of the pwm comparator for main rail output 49 fb error amplifier voltage feedback for main rail output 50 diff output of the main rail differential remote sense amplifier. 51 vsp differential output voltage sense positive for mail rail 52 vsn differential output voltage sense negative for main rail 53 agnd
ncp81243 www. onsemi.com 9 table 2. absolute maximum ratings pin symbol v max v min i source i sink comp,compa vcc + 0.3 v ?0.3 v 2 ma 2 ma cscomp, cscompa vcc + 0.3 v ?0.3 v 2 ma 2 ma diff, diffa vcc + 0.3 v ?0.3 v 2 ma 2 ma pwm1, pwm2, pwm3, pwm1a, pwm2a vcc + 0.3 v ?0.3 v vsn, vsna gnd + 300 mv gnd?300 mv 1 ma 1 ma vrdy vcc + 0.3 v ?0.3 v 2 ma 2 ma vcc 6.5 v ?0.3 v vrmp +25 v ?0.3 v all other pins vcc + 0.3 v ?0.3 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. *all signals referenced to gnd unless noted otherwise. table 3. thermal information description symbol value unit thermal characteristic qfn package (note 1) r ja 68 c/w operating junction temperature range (note 2) t j ?40 to +125 c operating ambient temperature range ?40 to +100 c maximum storage temperature range t stg ?40 to +150 c moisture sensitivity level qfn package msl 1 *the maximum package power dissipation must be observed. 1. jesd 51?5 (1s2p direct?attach method) with 0 lfm 2. jesd 51?7 (1s2p direct?attach method) with 0 lfm
ncp81243 www. onsemi.com 10 table 4. ncp81243 (3+2) electrical characteristics unless otherwise stated: ?40 c < t a < 100 c; 4.75 v < vcc < 5.25 v; c vcc = 0.1 f parameter test conditions min typ max unit error amplifier input bias current ?400 400 na open loop dc gain cl = 20 pf to gnd, rl = 10 k to gnd 80 db open loop unity gain bandwidth cl = 20 pf to gnd, rl = 10 k to gnd 20 mhz slew rate vin = 100 mv, g = ?10 v/v, vout = 0.75 v ? 1.52 v, cl = 20 pf to gnd, dc load = 10 k to gnd 20 v/ s maximum output voltage i source = 2.0 ma 3.5 ? ? v minimum output voltage i sink = 0.5 ma ? ? 1 v differential summing amplifier input bias current ?400 ? 400 na vsp input voltage range ?0.3 ? 3.0 v vsn input voltage range ?0.3 ? 0.3 v ?3 db bandwidth cl = 20 pf to gnd, rl = 10 k to gnd 12 mhz closed loop dc gain vs to diff vs+ to vs? = 0.5 to 1.3 v 1.0 v/v droop accuracy csref?droop = 80 mv dac = 0.8 v to 1.2 v ?82 ?78 mv maximum output voltage i source = 2 ma 3.0 ? ? v minimum output voltage i sink = 0.5 ma ? ? 0.5 v current summing amplifier offset voltage (vos) ?500 500 v input bias current cssum = csref = 1 v ?7.5 7.5 a open loop gain 80 db current sense unity gain bandwidth c l = 20 pf to gnd, r l = 10 k to gnd 10 mhz maximum cscomp (a) output volt- age isource = 2 ma 3.5 ? ? v minimum cscomp(a) output volt- age isink = 500 a ? ? 0.1 v current balance amplifier input bias current cspx = csnx = 1.2 v ?50 ? 50 na common mode input voltage range cspx = csnx 0 ? 2.0 v differential mode input voltage range csnx = 1.2 v ?100 ? 100 mv closed loop input offset voltage matching cspx = 1.2 v, measured from the average ?2 ? 2 mv current sense amplifier gain 0 v < cspx < 0.1 v 5.7 6.0 6.3 v/v multiphase current sense gain matching csnx = cspx = 10 mv to 30 mv ?4.5 4.5 % ?3 db bandwidth guaranteed by simulation 8 mhz bias supply supply voltage range 4.75 5.25 v vcc quiescent current ps0 50 ma vcc quiescent current ps1 50 ma
ncp81243 www. onsemi.com 11 table 4. ncp81243 (3+2) electrical characteristics unless otherwise stated: ?40 c < t a < 100 c; 4.75 v < vcc < 5.25 v; c vcc = 0.1 f parameter unit max typ min test conditions bias supply vcc quiescent current ps2 50 ma vcc quiescent current ps3 20 ma vcc quiescent current ps4 (25 c only) 230 a vcc quiescent current enable low 45 a uvlo threshold vcc rising 4.5 v vcc falling 4 vcc uvlo hysteresis 200 mv vrmp supply range 4.5 20 v uvlo threshold vrmp rising 4.2 v vrmp falling 3 vcc uvlo hysteresis 700 mv dac slew rate soft start slew rate 1/2 sr fast mv/ s slew rate slow 1/2 sr fast mv/ s slew rate fast >10 mv/ s aux soft start slew rate 1/2 sr fast mv/ s aux slew rate slow 1/2 sr fast mv/ s aux slew rate fast >10 mv/ s enable input enable high input leakage current enable = 0 ?1 0 1.0 a upper threshold v upper 0.8 v lower threshold v lower 0.3 v enable delay time measure time from enable transitioning hi, vboot is not 0 v 2.5 ms dron output high voltage sourcing 500 a 3.0 ? ? v output low voltage sinking 500 a ? ? 0.1 v pull up resistances 2.0 k rise/fall time cl (pcb) = 20 pf, vo = 10% to 90% ? 160 ns internal pull down resistance vcc = 0 v 70 k iout /iouta output input referred offset voltage i limit to csref ?3 +3 mv output current max ilimit sink current 80 a ? ? 800 a current gain (iout current)/(ilimit current) rlim = 20 k, riout = 5 k dac = 0.8 v, 1.25 v, 1.52 v 9.5 10 10.5 oscillator switching frequency range 300 ? 1400 khz switching frequency accuracy 300 khz < fsw < 1.4 mhz ?10 ? 10 % 3 phase operation 350 390 430 khz output over voltage & under voltage protection (ovp & uvp) over voltage threshold during soft?start 2.5 v
ncp81243 www. onsemi.com 12 table 4. ncp81243 (3+2) electrical characteristics unless otherwise stated: ?40 c < t a < 100 c; 4.75 v < vcc < 5.25 v; c vcc = 0.1 f parameter unit max typ min test conditions output over voltage & under voltage protection (ovp & uvp) over voltage threshold above dac vss rising 375 400 425 mv over voltage delay vss rising to pwmx low 50 ns under voltage threshold below dac?droop vss falling 275 300 325 mv under?voltage hysteresis vss rising 25 mv under?voltage delay 5 s overcurrent protection ilim threshold current (ocp shutdown after 50 us delay) main rail, rlim = 20 k 8.0 10 12 a ilim threshold current (immediate ocp shutdown) main rail, rlim = 20 k 13 15 16.5 a ilim threshold current (ocp shutdown after 50 s delay) main rail, rlim = 20 k (n = number of phases in ps0 mode) 10/n a ilim threshold current (immediate ocp shutdown) main rail, rlim = 20 k (n= number of phases in ps0 mode) 15/n a ilim threshold current (ocp shutdown after 50 s delay) auxiliary rail, rlim = 20 k 8.0 10 11 a ilim threshold current (immediate ocp shutdown) auxiliary rail, rlim = 20 k 13 15 16.5 a ilim threshold current (ocp shutdown after 50 s delay) auxiliary rail rlim = 20 k 10/n a ilim threshold current (immediate ocp shutdown) auxiliary rail, rlim = 20 k 15/n a modulators (pwm comparators) for main rail & auxiliary rail minimum pulse width fsw = 350 khz 60 ns 0% duty cycle comp voltage when the pwm outputs remain lo 1.3 ? v 100% duty cycle comp voltage when the pwm outputs remain hi vrmp = 12.0 v ? 2.5 ? v pwm ramp duty cycle matching comp = 2 v, pwm ton matching 1 % pwm phase angle error between adjacent phases 5 deg ramp feed?forward voltage range 4.5 20 v tsense/tsensea vrhot assert threshold 440 mv vrhot rising threshold 460 mv alert rising threshold 480 mv alert assertion threshold 460 mv tsense bias current ?57.5 ?60 ?62.5 a vrhot output low voltage 0.3 v output leakage current high impedance state ?1.0 ? 1.0 a adc voltage range 0 2 v total unadjusted error (tue) ?1.25 +1.25 % differential nonlinearity (dnl) 8?bit 1 lsb power supply sensitivity 1 % conversion time 30 s
ncp81243 www. onsemi.com 13 table 4. ncp81243 (3+2) electrical characteristics unless otherwise stated: ?40 c < t a < 100 c; 4.75 v < vcc < 5.25 v; c vcc = 0.1 f parameter unit max typ min test conditions adc round robin 90 s vrdy output output low saturation voltage i vdd(a)_vrdy = 4 ma ? ? 0.3 v rise time external pull?up of 1k to 3.3v, c tot = 45 pf, vo = 10% to 90% 150 ns fall time external pull?up of 1 k to 3.3 v, c tot = 45 pf, vo = 90% to 10% 150 ns output voltage at power?up vrdy pulled up to 5 v via 2 k enable low ? ? 0.1 v output leakage current when high vrdy = 5.0 v ?1.0 ? 1.0 a vrdy delay (falling) from ocp ? 50 ? s from ovp 300 ns pwm (a), outputs output high voltage sourcing 500 a vcc ? 0.2v ? ? v output mid voltage no load 1.9 2.0 2.1 v output low voltage sinking 500 a ? ? 0.7 v rise and fall time cl (pcb) = 50 pf, vo =10% to 90% of vcc ? 10 ns tri?state output leakage gx = 2.0v, x = 1?2, en=low ?1.0 ? 1.0 a phase detection csp2, csp3, csp1a, csp2a pin threshold voltage 4.7 v phase detect timer 100 s 3. guaranteed by design or characterization. not in production testing
ncp81243 www. onsemi.com 14 table 5. state truth table state vr_rdy pin error amp comp pin ovp & uvp dron pin method of reset por 0threshold low low disabled low start up delay & calibration en> threshold uvlo>threshold low low disabled low dron fault en> threshold uvlo>threshold dron threshold uvlo >threshold dron > high low operational active / no latch high normal operation en > threshold uvlo >threshold dron > high high operational active / latching high n/a over voltage low n/a dac+ovp high over current low operational last dac code low v out = 0 v low: if reg34h:bit0=0; high:if reg34h:bit0=1; clamped at 0.9 v disabled high, pwm outputs in low state
ncp81243 www. onsemi.com 15 controller por disable vcc > uvlo calibrate drive off phase detect soft start ramp normal vr _ rdy ovp uvp en = 1 3 . 5 ms and cal done vccp > uvlo and dron high en = 0 vs > ovp vdrp > ilim no _ cpu invalid vid vs < uvp vs > uvp dac = vid vcc < uvlo soft start ramp dac = vboot general the ncp81243 is a dual rail three plus two phase dual edge modulated multiphase pwm controller, with a single serial intel proprietary interface control interface. ultrasonic mode: the switching frequency of a rail in dcm will decrease at very light loads. ultrasonic mode forces the switching frequency to stay above the audible frequency range. phase configuration: the ncp81243 has 5 external pwm signals which can be configured across the two rail. a resistor to ground on pin10, is used to configure phase configuration, frequency double on main/auxiliary rail and sr. available configuration options from pin10 are shown below:
ncp81243 www. onsemi.com 16 table 6. phase configuration selection resistor level ph_config boost main rail boost aux rail sr 10000 1 3+2 no no 10 13000 2 3+2 no no 30 16000 3 3+2 no no 10 19200 4 3+2 no no 30 22500 5 3+2 no yes(*2) 10 26000 6 3+2 no yes(*2) 30 29600 7 3+2 no yes(*2) 10 33500 8 3+2 no yes(*2) 30 37400 9 3+2 yes(*2) no 10 41500 10 3+2 yes(*2) no 30 45800 11 3+2 yes(*2) no 10 50200 12 3+2 yes(*2) no 30 54800 13 3+2 yes(*2) yes(*2) 10 59500 14 3+2 yes(*2) yes(*2) 30 64500 15 3+2 yes(*2) yes(*2) 10 69600 16 3+2 yes(*2) yes(*2) 30 75000 17 4+1 no no 10 80600 18 4+1 no no 30 86500 19 4+1 no no 10 92600 20 4+1 no no 30 99000 21 4+1 no yes(*2) 10 105500 22 4+1 no yes(*2) 30 112500 23 4+1 no yes(*2) 10 119600 24 4+1 no yes(*2) 30 127000 25 4+1 yes (*1.5) no 10 134800 26 4+1 yes(*1.5) no 30 143000 27 4+1 yes(*1.5) no 10 151400 28 4+1 yes(*1.5) no 30 160300 29 4+1 yes(*1.5) yes(*2) 10 169500 30 4+1 yes(*1.5) yes(*2) 30 180000 31 4+1 yes(*1.5) yes(*2) 10 210000 32 4+1 yes(*1.5) yes(*2) 30
ncp81243 www. onsemi.com 17 phase interleaving pwm1 0 pwm2a 270 pwm2 120 pwm3 240 pwm1a 90 3+2 pwm1 pwm2 pwm3 pwm1a pwm2a o o o o o pwm1 0 pwm2a 270 pwm2 120 pwm1a 90 2+2 pwm1 pwm2 pwm1a pwm2a o o o o serial vid interface (intel proprietary interface) information regarding intel proprietary interface can be obtained from intel.
ncp81243 www. onsemi.com 18 vboot and intel proprietary interface address programming the ncp81243 has a vboot voltage register that can be externally programmed for both core and auxiliary boot?up output voltages. the vboot voltage for main and auxiliary rails can be programmed with a resistor from vboot and vboota pin to gnd. in addition to vboot level, pin 28 and pin 29 also support intel proprietary interface bus address programming. the ncp81243 support multiple intel proprietary interface device addresses per rail. pin 28 (vboot/addr) is used to set the address for the main rail, pin 29 (vboota/addra) is used to address the auxiliary rail. on power up a 10 a current is sourced from these pins through a resistor connected to this pin and the resulting voltage is measured. table 7 shows the resistor values that should be used and the corresponding intel proprietary interface and vboot options for each rail. pin 28 (vboot/addr) resistor level vboot address auto phase shedding disabling 10000 1 0 0 no 15000 2 0 0 yes 21000 3 1.2 0 no 26700 4 0.9 0 no 33200 5 0 1 no 41200 6 0 1 yes 49900 7 1.2 1 no 60400 8 0.9 1 no 71500 9 0 2 no 84500 10 0 2 yes 97600 11 1.2 2 no 115000 12 1.5 2 no 133000 13 0 4 no 154000 14 0 4 yes 178000 15 1.2 4 no 210000 16 1.5 4 no table 7. vboot, address programmability main and aux rails pin 27 (vboota/addra) resistor level vboot aux address aux 10000 1 0 1 13000 2 1.05 1 15800 3 1.2 1 20000 4 0.9 1 23700 5 0 0 28000 6 1.05 0 33200 7 1.2 0 38300 8 0.9 0 45000 9 0 2 52300 10 1.05 2 60400 11 1.2 2 69800 12 1.5 2 80600 13 0 3 93100 14 1.05 3 107000 15 1.2 3 121000 16 1.5 3 137000 17 0.8 2 158000 18 0.95 2 180000 19 0.8 3 210000 20 0.95 3
ncp81243 www. onsemi.com 19 remote sense amplifier a high performance high input impedance true differential amplifier is provided to accurately sense the output voltage of the regulator. the vsp and vsn inputs should be connected to the regulator?s output voltage sense points. the remote sense amplifier takes the difference of the output voltage with the dac voltage and adds the droop voltage to v difout = v vsp v vsn 1.3 v v dac v droop v csref this signal then goes through a standard error compensation network and into the inverting input of the error amplifier. the non?inverting input of the error amplifier is connected to the same 1.3 v reference used for the differential sense amplifier output bias. high performance voltage error amplifier a high performance error amplifier is provided for high bandwidth transient performance. a standard type iii compensation circuit is normally used to compensate the system. differential current feedback amplifiers each phase has a low offset dif ferential amplifier to sense that phase current for current balance. the inputs to the csnx and cspx pins are high impedance inputs. it is recommended that any external filter resistor rcsn does not exceed 10 k to avoid offset issues with leakage current. it is also recommended that the voltage sense element be no less than 0.5 k for accurate current balance. fine tuning of this time constant is generally not required. the individual phase current is summed into the pwm comparator feedback this way current is balanced via a current mode control approach. ccsn rcsn dcr lphase 1 2 swnx vout cspx csnx r csn l phase c csn dcr total current sense amplifier the ncp81243 uses a patented approach to sum the phase currents into a single temperature compensated total current signal. this signal is then used to generate the output voltage droop, total current limit, and the output current monitoring functions. the total current signal is floating with respect to csref. the current signal is the difference between cscomp and csref. the ref(n) resistors sum the signals from the output side of the inductors to create a low impedance virtual ground. the amplifier actively filters and gains up the voltage applied across the inductors to recover the voltage drop across the inductor series resistance (dcr). rth is placed near an inductor to sense the temperature of the inductor. this allows the filter time constant and gain to be a function of the rth ntc resistor and compensate for the change in the dcr with temperature. the dc gain equation for the current sensing: v cscomp?csref rcs2 rcs1 rth rcs1 rth rph iout total dcr set the gain by adjusting the value of the rph resistors. the dc gain should be set to the output voltage droop. if the voltage from cscomp to csref is less than 100 mv at iccmax then it is recommend increasing the gain of the cscomp amp. this is required to provide a good current signal to offset voltage ratio for the ilimit pin. when no droop is needed, the gain of the amplifier should be set to provide ~100 mv across the current limit programming resistor at full load. the values of rcs1 and rcs2 are set based on the 100k ntc and the temperature effect of the inductor and should not need to be changed. the ntc should be placed near the closest inductor. the output voltage droop should be set with the droop filter divider. the pole frequency in the cscomp filter should be set equal to the zero from the output inductor. this allows the circuit to recover the inductor dcr voltage drop current signal. ccs1 and ccs2 are in parallel to allow for fine tuning of the time constant using commonly available values. it is best to fine tune this filter during transient testing.
ncp81243 www. onsemi.com 20 f z dcr@25c 2 pi l phase programming the current limit the current limit thresholds are programmed with a resistor between the ilimit and cscomp pins. the ilimit pin mirrors the voltage at the csref pin and mirrors the sink current internally to iout (reduced by the iout current gain) and the current limit comparators. the 100% current limit trips if the ilimit sink current exceeds 10 a for 50 s. the 150% current limit trips with minimal delay if the ilimit sink current exceeds 15 a. set the value of the current limit resistor based on the cscomp?csref voltage as shown below. r limit rcs2 rcs1 rth rcs1 rth rph iout limit dcr 10 or r limit v cscomp?csref @ ilimit 10 programming dac feed?forward filter the dac feed?forward implementation is realized by having a filter on the vsn pin. programming rvsn sets the gain of the dac feed?forward and cvsn provides the time constant to cancel the time constant of the system per the following equations. cout is the total output capacitance and rout is the output impedance of the system. rvsn cout rout 453.6 10 6 cvsn rout cout rvsn programming droop an output loadline is a power supply characteristic wherein the regulated (dc) output voltage decreases proportional to the load current. this characteristic can reduce the output capacitance required to maintain output voltage within limits during load transient faster than those to which the regulation loop can respond. with the ncp81243 and projects the loadline is produced by adding a signal proportional to output load current (vdroop) to the output voltage feedback signal? thereby satisfying the voltage regulator at an output voltage reduced proportional to load current. the loadline is programmed by setting the gain of the total current sense amplifier such that the total current signal is equal to the desired output voltage droop.the signals cscomp and csref are differentially summed with the output voltage feedback to add precision voltage droop to the output voltage. droop = dcr * (r cs / r ph ) programming iout the iout pin sources a current in proportion to the ilimit sink current. the voltage on the iout pin is monitored by the internal a/d converter and should be scaled with an external resistor to ground such that a load equal to iccmax generates a 2 v signal on iout. a pull?up resistor from 5 v vcc can be used to offset the iout signal positive if needed. r iout 2.0 v r limit 10 rcs2 rcs1 rth rcs1 rth rph iout icc_max dcr programming icc_max a resistor to ground on the imax pin programs these registers at the time the part is enabled. 10 ua is sourced from these pins to generate a voltage on the program resistor. icc_max 21h r 10 a 255 a 2v programming tsense a temperature sense input per rail is provided. a precision current is sourced out the output of the tsense pin to generate a voltage on the temperature sense network. the voltage on the temperature sense inputs are sampled by the internal a/d converter. a 100 k ntc similar to the vishay ert?j1vs104ja should be used. rcomp1 is optional to the user, and can be used to slightly change the hysteresis. see the specification table for the thermal sensing voltage thresholds and source current.
ncp81243 www. onsemi.com 21 rcomp2 8.2k rntc 100k cfilter 0.1uf agnd agnd rcomp1 0.0 tsense precision oscillator a programmable precision oscillator is provided. the clock oscillator serves as the master clock to the ramp generator circuit. this oscillator is programmed by a resistor to ground on the rosc pin. the oscillator frequency range is between 300 khz/phase to 1.4 mhz/phase. the rosc pin provides approximately 2 v out and the source current is mirrored into the internal ramp oscillator. the oscillator frequency is approximately proportional to the current flowing in the rosc resistor. figure 7. ncp81243 operating frequency vs. rosc the oscillator generates triangle ramps that are 1.3~2.5 v in amplitude depending on the vrmp pin voltage to provide input voltage feed forward compensation. the ramps are equally spaced out of phase with respect to each other and the signal phase rail is set half way between phases 1 and 2 of the multi phase rail for minimum input ripple current. for use with on semiconductors phase doubler the ncp81243 of fers the user the ability to double the frequency of each rail independently or simultaneously. this will allow the rail that is being doubled to maintain a higher system switching frequency. programming the ramp feed?forward circuit the ramp generator circuit provides the ramp used by the pwm comparators. the ramp generator provides voltage feed?forward control by varying the ramp magnitude with respect to the vrmp pin voltage. the vrmp pin also has a 4v uvlo function. the vrmp uvlo is only active after the controller is enabled. the vrmp pin is high impedance input when the controller is disabled. the pwm ramp time is changed according to the following, v ramppk pk pp 0.1 v vrmp vin comp ? il duty vramp _pp
ncp81243 www. onsemi.com 22 pwm comparators the noninverting input of the comparator for each phase is connected to the summed output of the error amplifier (comp) and each phase current (i l *dcr*phase balance gain factor). the inverting input is connected to the oscillator ramp voltage with a 1.3 v offset. the operating input voltage range of the comparators is from 0 v to 3.0 v and the output of the comparator generates the pwm output. during steady state operation, the duty cycle is centered on the valley of the sawtooth ramp waveform. the steady state duty cycle is still calculated by approximately vout/vin. during a transient event, the controller will operate in a hysteretic mode with the duty cycles pull in for all phases as the error amp signal increases with respect to all the ramps. phase detection sequence normally, ncp81243 operates as a 3?phase vcore/ 2?phase auxiliary pwm controller however the ncp81243 can also be configures as a 4+1?phase controller. during start?up, the number of operational phases and their phase relationship is determined by the internal circuitry monitoring the csp outputs. configuration phase configuration programming pin phase config (30 mv/us slew rate) programming pin cspx unused pins 1 4+1 80k6 all csp pins connected normally 2 4+0 80k6 connect csp1a to vcc through a 2 k resistor. all other csp pins connected normally float:pwm1a, ilima, diffouta,compa,cscompa ground: iouta, fba, cssuma, csrefa,vspa, tsensea 3 3+2 13k all csp pins connected normally no unused pins 4 3+1 13k connect csp2a to vcc through a 2k resistor. all other csp pins connected normally float: pwm2a 5 3+0 13k connect csp2a and csp1a to vcc through a 2k resistor. all other csp pins connected normally float: pwm3a, pwm2a, pwm1a, ilima, diffouta, compa, cscompa ground: iouta, fba, cssuma, csrefa, vspa, tsensea 6 2+2 13k connect csp3 to vcc through a 2k resistor pulled to vcc. all other csp pins connected normally float: pwm3 7 2+1 13k connect csp2a to vcc through a 2k resistor. all other csp pins connected normally float pwm3, pwm2a 8 2+0 13k connect csp3, csp2a and csp1a to vcc through a 2k resistor. all other csp pins connected normally float pwm3, pwm1a, pwm2a, pwm3ilima, diffouta, compa, cscompa ground: iouta, fba, cssuma, csrefa, vspa, tsensea 9 1+2 13k connect csp3 and csp2 through a 2k resistor pulled to vcc. all other csp pins connected normally float: pwm2 and pwm3 10 1+1 13k connect csp3, csp2 and csp2a through a 2k resistor pulled to vcc. all other csp pins connected normally float: pwm2, pwm3, pwm2a 11 1+0 13k connect csp3, csp2, csp2a and csp1a through a 2k resistor pulled to vcc. all other csp pins connected normally float: pwm2, pwm3, pwm1a, pwm2a, pwm3a, ilima, diffouta, compa, cscompa ground: iouta, fba, cssuma, csrefa, vspa, vsna the pwm outputs are logic?level devices intended for driving fast response external gate drivers such as the ncp81151 and ncp81161. as each phase is monitored independently, operation approaching 100% duty cycle is possible. in addition, more than one pwm output can be on at the same time to allow overlapping phases.
ncp81243 www. onsemi.com 23 protection features under voltage lockouts there are several under voltage monitors in the system. hysteresis is incorporated within the comparators. ncp81243 monitors the 5 v vcc supply. the gate driver monitors both the gate driver vcc and the bst voltage. when the voltage on the gate driver is insufficient it will pull dron low and prevents the controller from being enabled. the gate driver will hold dron low for a minimum period of time to allow the controller to hold off it?s startup sequence. in this case the pwm is set to the mid state to begin soft start. dac gate driver pulls dron low during driver uvlo and calibration if dron is pulled low the controller will hold off its startup figure 8. gate driver uvlo restart start up sequence following the rise of vcc and vrmp above the uvlo thresholds, externally programmed data is collected. after the configuration data is collected, the pwms will be set to 2.0 v mid state to indicate that the drivers should be in diode mode. when the device is enabled dron will then be asserted high to activate the gates, please note that there is only one enable pin, once this enable is pulled high both the main and auxiliary rail is enabled at this time. a digital counter steps the dac up from zero to the target voltage level based on the soft start slew rate selected. as the dac ramps the pwm outputs for each rail will begin to fire. each phase will move out of the mid state when the first pwm pulse is produced. when the controller is disabled the pwm signal will return to the mid state. when the controller is disabled, the pwm signals will return to mid ? level. figure 9. startup operation
ncp81243 www. onsemi.com 24 over current latch?off protection the ncp81243 compares a programmable current?limit set point to the voltage from the output of the current?summing amplifier. the level of current limit is set with the resistor from the ilim pin to cscomp. the current through the external resistor connected between ilim and cscomp is then compared to the internal current limit current i cl . if the current generated through this resistor into the ilim pin (ilim) exceeds the internal current?limit threshold current (i cl ), an internal latch?off counter starts, and the controller shuts down if the fault is not removed after 50 s (shut down immediately for 150% load current) after which the outputs will remain disabled until the vcc voltage or en is toggled. the voltage swing of cscomp cannot go below ground. this limits the voltage drop across the dcr through the current balance circuitry. an inherent per?phase current limit protects individual phases if one or more phases stop functioning because of a faulty component. the over?current limit is programmed by a resistor on the ilim pin. the resistor value can be calculated by the following equations. equation related to the ncp81243: r ilim i lim dcr r cs r ph i cl where i cl = 10 a r ph r cs rlim ilim cscomp cssum r ph r ph csref input under?voltage lockouts ncp81243 monitors the 5 v vcc supply as well as the vrmp pin. hysteresis is incorporated within these comparators. if either the vcc or the vrmp uvlo requirements are not met the vr will fail to startup and the intel proprietary interface interface will be unresponsive to all commands. under voltage monitor the output voltage is monitored at the output of each differential amplifier for uvlo. if the output falls more than 300 mv below the dac?droop voltage the uvlo comparator will trip sending the vr_rdy signal low. over voltage protection the output voltage for each rail is also monitored for ovp at the output of the differential amplifier and also at the csref pin. during normal operation, if the output voltage exceeds the dac voltage by 400 mv, the vr_rdy flag goes low, and the output voltage will be ramped down to 0 v, the ramp to 0 v is controlled to avoid producing negative output voltage. at the same time, the pwms of the ovp rail are sent low. the pwm outputs will pulse to mid level during the dac ramp down period if the output decreases below the dac+ovp threshold as dac decreases. when the dac reaches 0 v, the pwms will be held low, the high side gate drivers are all turned off and the low side gate drivers are all turned on. the part will stay in this mode until the vcc voltage or en is toggled.
ncp81243 www. onsemi.com 25 figure 10. ovp behavior at startup figure 11. ovp during normal operation mode during start up, the ovp threshold is set to 2.5 v. this allows the controller to start up without false triggering the ovp
ncp81243 www. onsemi.com 26 package dimensions qfn52 6x6, 0.4p case 485be issue b seating note 4 k 0.10 c (a3) a a1 d2 b 1 14 27 52 e2 52x l bottom view detail c top view side view d a b e 0.10 c pin one location 0.10 c 0.08 c c 40 e a 0.07 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal tip 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.15 0.25 d 6.00 bsc d2 4.60 4.80 e 6.00 bsc 4.80 e2 4.60 e 0.40 bsc l 0.25 0.45 l1 0.00 0.15 note 3 plane dimensions: millimeters 0.25 4.80 0.40 4.80 52x 0.63 52x 6.40 6.40 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* detail b l1 detail a l alternate terminal constructions l 0.30 ref pitch 52x pkg outline l2 0.15 ref l2 detail c 8 places l2 detail a detail d 8 places 0.11 0.4 9 detail d on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp81243/d intel is a registered trademark of intel corporation in the u.s. and/or other countries. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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